DC/DC CONVERTER

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
1
ORDERING INFORMATION
DESCRIPTION
The SC1162/3 combines a synchronous voltage mode
controller with a low-dropout linear regulator providing
most of the circuitry necessary to implement two DC/
DC converters for powering advanced microprocessors
such as Pentium® II.
The SC1162/3 switching section features an integrated
5 bit D/A converter, pulse by pulse current limiting,
integrated power good signaling, and logic compatible
shutdown. The SC1162/3 switching section operates at
a fixed frequency of 200kHz, providing an optimum
compromise between size, efficiency and cost in the
intended application areas. The integrated D/A converter
provides programmability of output voltage from
2.0V to 3.5V in 100mV increments and 1.30V to 2.05V
in 50mV increments with no external components.
The SC1162/3 linear section is a high performance
positive voltage regulator design for either the GTL bus
supply at 1.5V (SC1162) or an adjustable output
(SC1163).
The output of the linear regulator can provide up to 5A
or more with the appropriate external MOSFET.
Pentium is a registered trademark of Intel Corporation
PIN CONFIGURATION
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
BLOCK DIAGRAM
FEATURES
• Synchronous design, enables no heatsink solution
• 95% efficiency (switching section)
• 5 bit DAC for output programmability
• On chip power good function
• Designed for Intel Pentium® II requirements
• 1.5V or Adj. @ 1% for linear section
• 1.300V-2.05V ±1.5%; 2.100V-3.500V ±2%
APPLICATIONS
• Pentium® ll or Deschutes microprocessor supplies
• Flexible motherboards
• 1.3V to 3.5V microprocessor supplies
• Programmable dual power supplies
Part Number(1) Package
Linear
Voltage
Temp.
Range (TJ)
SC1162CSW SO-24 1.5V 0° to 125°C
SC1163CSW SO-24 Adj. 0° to 125°C
Note:
(1) Add suffix ‘TR’ for tape and reel.
Top View
(24 Pin SOIC)
LDOV GATE LDOS
PGNDL
DL
BSTL
PGNDH
DH
BSTH
VCC CS- CS+ EN
VID3
VID4
VID2
VID0
VID1
VOSENSE
PWRGOOD
OVP
VCC
70mV
1.25 REF CURRENT LIMIT
D/A &
LEVEL SHIFT
AND HIGH SIDE
MOSFET DRIVE
SHUTDOWN
LOGIC
OSCILLATOR
R
S
Q
SHOOTTHRU
CONTROL
SYNCHRONOUS
MOSFET DRIVER
ERROR
AMP
AGND
FET
CONTROLLER
1.265V
REF
OPEN
COLLECTORS
VCC
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
2
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CSp-CSm) < 60mV; LDOV = 11.4V to 12.6V; TA = 25oC
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Section
Output Voltage IO = 2A See Note 1.
Supply Voltage VCC 4.2 7 V
Supply Current VCC = 5.0 8 15 mA
Load Regulation IO = 0.8A to 15A 1 %
Line Regulation 0.5 %
Minimum operating voltage 4.2 V
Current Limit Voltage 55 70 85 mV
Oscillator Frequency 175 200 225 kHz
Oscillator Max Duty Cycle 90 95 %
DH Sink/Source Current BSTH-DH = 4.5V, DH-PGNDH = 2V 1 A
DL Sink/Source Current BSTL-DL = 4.5V, DL-PGNDL = 2V 1 A
Output Voltage Tempco 65 ppm/oC
Gain (AOL) VOSENSE to VO 35 dB
OVP threshold voltage 120 %
OVP source current VOVP = 3.0V 10 mA
Power good threshold voltage 85 115 %
Dead time 50 100 ns
Linear Section
Quiescent current LDOV = 12V 5 mA
Output Voltage (SC1162) 1.485 1.500 1.515 V
Reference Voltage (SC1163) 1.252 1.265 1.278 V
Feedback Pin Bias Current (SC1163) 10 uA
Gain (AOL) LDOS to GATE 90 dB
Load Regulation IO = 0 to 8A(2) 0.3 %
Line Regulation 0.3 %
Output Impedance 200 Ω
Parameter Symbol Maximum Units
VCC to GND VIN -0.3 to +7 V
PGND to GND ± 1 V
BST to GND -0.3 to +15 V
Operating Temperature Range TA 0 to +70 °C
Junction Temperature Range TJ 0 to +125 °C
Storage Temperature Range TSTG -65 to +150 °C
Lead Temperature (Soldering) 10 seconds TL 300 °C
Thermal Impedance Junction to Ambient θJA 80 °C/W
Thermal Impedance Junction to Case θJC 25 °C/W
ABSOLUTE MAXIMUM RATINGS
Notes: (1) See Output Voltage table
(2) In application circuit
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
3
Note:
(1) All logic level inputs and outputs are open
collector TTL compatible.
PIN DESCRIPTION
Pin Pin Name Pin Function
1 AGND Small Signal Analog and Digital Ground
2 NC No connection
3 NC No Connection
4 LDOS Sense Input for LDO
5 VCC Input Voltage
6 OVP High Signal out if VO>setpoint +20%
7 PWRGOOD(1)
Open collector logic output, high if VO
within 10% of setpoint
8 CS- Current Sense Input (negative)
9 CS+ Current Sense Input (positive)
10 PGNDH Power Ground for High Side Switch
11 DH High Side Driver Output
12 PGNDL Power Ground for Low Side Switch
13 DL Low Side Driver Output
14 BSTL Supply for Low Side Driver
15 BSTH Supply for High Side Driver
16 EN(1) Logic low shuts down the converter;
High or open for normal operation.
17 VOSENSE Top end of internal feedback chain
18 VID4(1) Programming Input (MSB)
19 VID3(1) Programming Input
20 VID2(1) Programming Input
21 VID1(1) Programming Input
22 VID0(1) Programming Input (LSB)
23 LDOV +12V for LDO section
24 GATE Gate Drive Output LDO
Top View
(24 Pin SOIC)
AGND GATE
LDOS
NC
VCC
OVP
PWRGOOD
CSCS+
PGNDH
DH
PGNDL
1
2
3
LDOV
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VOSENSE
EN
BSTH
BSTL
DL
VID0
VID1
VID2
VID3
VID4
NC
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
4
OUTPUT VOLTAGE
Unless specified: VCC = 5.00V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CSp-CSm) < 60mV; TA = 25oC
PARAMETER CONDITIONS VID
43210
MIN TYP MAX UNITS
Output Voltage IO = 2A in Application Circuit 01111 1.281 1.300 1.320
01110 1.330 1.350 1.370
01101 1.379 1.400 1.421
01100 1.428 1.450 1.472
01011 1.478 1.500 1.523
01010 1.527 1.550 1.573
01001 1.576 1.600 1.624
01000 1.625 1.650 1.675
00111 1.675 1.700 1.726
00110 1.724 1.750 1.776
00101 1.773 1.800 1.827
00100 1.822 1.850 1.878
00011 1.872 1.900 1.929
00010 1.921 1.950 1.979
00001 1.970 2.000 2.030
00000 2.019 2.050 2.081
11111 1.960 2.000 2.040
11110 2.058 2.100 2.142
11101 2.156 2.200 2.244
11100 2.254 2.300 2.346
11011 2.352 2.400 2.448
11010 2.450 2.500 2.550
11001 2.548 2.600 2.652
11000 2.646 2.700 2.754
10111 2.744 2.800 2.856
10110 2.842 2.900 2.958
10101 2.940 3.000 3.060
10100 3.038 3.100 3.162
10011 3.136 3.200 3.264
10010 3.234 3.300 3.366
10001 3.332 3.400 3.468
10000 3.430 3.500 3.570
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
5
VCC_CORE
VLIN
VID0 GND
VID1
VID2
VID3
VID4
12V
5V
EN
OVP
PWRGD
5V
C1
0.1uF
L1
4uH
R4
5mOhm
C18
0.1uF
+
C14
1500uF
+
C15
1500uF
+
C16
1500uF
+
C17
1500uF
+
C3
1500uF
+
C2
1500uF
R1
10 C13
0.1uF
Q2
BUK556
Q1
BUK556
C5
0.1uF
Q3
BUK556
+
R17
100K
+
C12
330uF
R5
2.32k
U1
SC1162/3CSW
AGND
1
VCC
5
OVP
6
PWRGOOD
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VO SENSE
17
VID4
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
NC
24 GATE
2 LDOV 23
LDOS
3
NC
4
R6
1.00k
R12
R13
R16
10k
NOTES: FOR SC1162, R12 AND R13 ARE NOT REQUIRED
CONNECT LDOS (PIN4) DIRECTLY TO VLIN
TO GENERATE 1.5V OUTPUT.
+
C21
330uF
*
*
* SEE "SETTING LDO OUTPUT VOLTAGE" TABLE
R17 REQUIRED IF VINLIN CAN BE PRESENT
WITHOUT 12V BEING PRESENT
APPLICATION CIRCUIT
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
6
MATERIALS LIST
Qty. Reference Part/Description Vendor Notes
4 C1,C5,C13,C
18
0.1μF Ceramic Various
6 C2,C3,C14-
C17
1500μF/6.3V SANYO MV-GX or equiv. Low ESR
3 C11,C12,
C21
330μF/6.3V Various
1 L1 4μH 8 Turns 16AWG on MICROMETALS T50-52D core
3 Q1,Q2,Q3 See notes See notes FET selection requires trade-off between efficiency and
cost. Absolute maximum RDS(ON) = 22 mΩ for Q1,Q2
1 R4 5mΩ IRC OAR-1 Series
1 R5 2.32kΩ, 1%, 1/8W Various
1 R6 1kΩ, 1%, 1/8W Various
1 R1 10Ω, 5%, 1/8W Various
1 R12 1%, 1/8W Various See Table (Not required for SC1162)
1 R13 1%, 1/8W Various See Table (Not required for SC1162)
1 R17 100k, 5%, 1/8W Various Required if Voltage is applied to the linear FET without
12V applied to SC1162/3
1 U1 SC1162/3CSW SEMTECH
SETTING LDO OUTPUT VOLTAGE
RB RA
VO LDO R12 R13
3.45V 105Ω 182Ω
3.30V 105Ω 169Ω
3.10V 102Ω 147Ω
2.90V 100Ω 130Ω
2.80V 100Ω 121Ω
2.50V 100Ω 97.6Ω
1.50V 100Ω 18.7Ω significan t error
that the (I R ) term does not cause
R and R must be low enough so
See layout diagram for clarificat ion
R Bottom feedback resistor
R Top feedback resistor
I Feedback pin bias current
Where :
(I R )
R
1.265 (R R )
V
FB A
A B
B
A
FB
FB A
B
A B
OUT
⋅
=
=
=
= ⋅ + + ⋅
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
7
70%
75%
80%
85%
90%
95%
0 2 4 6 8 10 12 14 16
Io (Amps)
Efficiency
3.5V Std
3.5V Sync
3.5V Sync Lo Rds
Typical Efficiency at Vo=3.5V
70%
75%
80%
85%
90%
95%
0 2 4 6 8 10 12 14 16
Io (Amps)
Efficiency
2.5V Std
2.5V Sync
2.5V Sync Lo Rds
Typical Ripple, Vo=2.8V, Io=10A
70%
75%
80%
85%
90%
95%
0 2 4 6 8 10 12 14 16
Io (Amps)
Efficiency
2.8V Std
2.8V Sync
2.8V Sync Lo Rds
Typical Efficiency at Vo=2.8V
70%
75%
80%
85%
90%
95%
0 2 4 6 8 10 12 14 16
Io (Amps)
Efficiency
2.0V Std
2.0V Sync
2.0V Sync Lo Rds
Typical Efficiency at Vo=2.0V
Transient Response Vo=2.8V, Io=300mA to 10A
Typical Efficiency at Vo=2.5V
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
8
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1162/3 PWM
controller. High currents switching at 200kHz are present
in the application and their effect on ground plane
voltage differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such
as to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the input
capacitor and bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
as small as possible. This loop contains all the high current,
fast transition switching. Connections should be as
wide and as short as possible to minimize loop inductance.
Minimizing this loop area will a) reduce EMI, b)
lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and c) minimize
source ringing, resulting in more reliable gate
switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection between
the output inductor and the sense resistor should
be a wide trace or copper area, there are no fast voltage
or current transitions in this connection and length
is not so important, however adding unnecessary
impedance will reduce efficiency.
Vout
12V IN
5V Vo Lin
5V
4uH
5mOhm
+
Cout
+
Cin
10
Q2
0.1uF
Q3
+
Cout Lin
2.32k
1.00k
RB
RA
+
Cin Lin
SC1162/3
AGND
1
VCC
5
OVP
6
PWRGOOD
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VO SENSE
17
VID4
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
NC
24
GATE
2
LDOV
23
LDOS
3
NC
4 Q1
0.1uF
Heavy lines indicate
high current paths.
are not required. LDOS connects to
For SC1162, RA and RB
Vo Lin
Layout diagram for the SC1162/3
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
9
Vout
5V
+
+
4) The Output Capacitor(s) (Cout) should be located
as close to the load as possible, fast transient load
currents are supplied by Cout only, and connections
between Cout and the load must be short, wide copper
areas to minimize inductance and resistance.
5) The SC1162/3 is best placed over a quite ground
plane area, avoid pulse currents in the Cin, Q1, Q2
loop flowing in this area. PGNDH and PGNDL should
be returned to the ground plane close to the package.
The AGND pin should be connected to the ground
side of (one of) the output capacitor(s). If this is not
possible, the AGND pin may be connected to the
ground path between the Output Capacitor(s) and the
Cin, Q1, Q2 loop. Under no circumstances should
AGND be returned to a ground inside the Cin, Q1, Q2
loop.
6) Vcc for the SC1162/3 should be supplied from the
5V supply through a 10Ω resistor, the Vcc pin should
be decoupled directly to AGND by a 0.1μF ceramic
capacitor, trace lengths should be as short as possible.
7) The Current Sense resistor and the divider across
it should form as small a loop as possible, the traces
running back to CS+ and CS- on the SC1162/3 should
run parallel and close to each other. The 0.1μF capacitor
should be mounted as close to the CS+ and
CS- pins as possible.
8) Ideally, the ground for the LDO section should be
returned to the ground side of (one of) the switching
section output capacitor(s).
Currents in various parts of the power section
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
10
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the
most critical component. Because of fast transient load
current requirements in modern microprocessor core
supplies, the output capacitors must supply all transient
load current requirements until the current in the output
inductor ramps up to the new level. Output capacitor
ESR is therefore one of the most important criteria. The
maximum ESR can be simply calculated from:
Transient current step
Maximum transient voltage excursion
Where
=
=
≤
t
t
t
t
ESR
I
V
I
V
R
Each Capacitor Total
Technology C
(μF)
ESR
(mΩ)
Qty.
Rqd.
C
(μF)
ESR
(mΩ)
Low ESR Tantalum 330 60 6 2000 10
OS-CON 330 25 3 990 8.3
Low ESR Aluminum 1500 44 5 7500 8.8
( )IN O
t
ESR V V
I
R C
L ≤ −
OSC
IN
L L f
V
I
RIPPLE ⋅ ⋅
=
4
IN
O
COND O DS on
V
V
P I R
≈
= ⋅ ⋅
= duty cycle
where
( )
2
δ
δ
= ⋅ ⋅10−2 SW O IN P I V
4
( ) O IN r f OSC
SW
I V t t f
P
⋅ ⋅ + ⋅
=
RR RR IN OSC P = Q ⋅V ⋅ f
For example, to meet a 100mV transient limit with a
10A load step, the output capacitor ESR must be less
than 10mΩ. To meet this kind of ESR level, there are
three available capacitor technologies:
The choice of which to use is simply a cost /performance
issue, with Low ESR Aluminum being the
cheapest, but taking up the most space.
INDUCTOR - Having decided on a suitable type and
value of output capacitor, the maximum allowable
value of inductor can be calculated. Too large an inductor
will produce a slow current ramp rate and will
cause the output capacitor to supply more of the transient
load current for longer - leading to an output voltage
sag below the ESR excursion calculated above.
The maximum inductor value may be calculated from:
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maximum
will guarantee that the inductor current will ramp
fast enough to reduce the voltage dropped across the
ESR at a faster rate than the capacitor sags, hence ensuring
a good recovery from transient with no additional
excursions.
We must also be concerned with ripple current in the
output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced
by the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
Ripple current allowance will define the minimum permitted
inductor value.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a
combination of conduction losses, switching losses and
bottom FET body diode recovery losses.
a) Conduction losses are simply calculated as:
b) Switching losses can be estimated by assuming a
switching time, if we assume 100ns then:
or more generally,
c) Body diode recovery losses are more difficult to estimate,
but to a first approximation, it is reasonable to assume
that the stored charge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The resulting power dissipation in the top FET
will be:
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
11
FET type RDS(on) (mΩ) PD (W) Package
BUK556H 22 2.48 TO220
IRL2203 7.0 0.79 D2PAK
Si4410 13.5 1.53 SO-8
(1 ) ( )
= 2 ⋅ ⋅ −δ COND O DS on P I R
FET type RDS(on) (mΩ) PD (W) Package
BUK556H 22 1.95 TO220
IRL2203 7.0 0.62 D2PAK
Si4410 13.5 1.20 SO-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduction
at the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined
by:
For the example above:
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the surface
mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W
for the D2PAK and 80oC/W for the SO-8 are readily
achievable. The corresponding temperature rise is detailed
below:
Temperature rise (oC)
FET type Top FET Bottom FET
BUK556H 49.6(1) 39.0(1)
IRL2203 31.6 24.8
Si4410 122.4 96
(1) With 20oC/W Heatsink
It is apparent that single SO-8 Si4410 are not adequate for
this application, but by using parallel pairs in each position,
power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
INPUT CAPACITORS - since the RMS ripple current in
the input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may
be restrictions on input di/dt. These restrictions require
useable energy storage within the converter circuitry,
either as extra output capacitance or, more usually,
additional input capacitors. Choosing low ESR input
capacitors will help maximize ripple rating for a given
size.
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1162/3
© 1999 SEMTECH CORP.
October 25, 1999
652 MITCHELL ROAD NEWBURY PARK CA 91320
12
OUTLINE DRAWING
JEDEC MS-013AD
B17104B
ECN99-667
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.